i use the memory to implement parts of the algorithm (like transpose operation and flips etc. I'm now using internal memory (fpga mram and m4k) - but eventually i would have to use onboard ddrii memory. In the log i can see how much register levels it has inserted - when i do this separately i end up with approx 80 register levels, but when i do this on the entire project - all i get is less than 10.īecause of that i thought that synplify must have problems with large designs - and went on to splitting it. however - when i do this to every part on its own - i get the needed frequency (or higher), but when i pipeline the entire project - it fails to reach those frequencies. It is possible to pipeline - and i actually do use this. What about timing violations ? Did you achieve the required clock frequency ? ) ? Did you get still warnings regarding. Have a look to the resource utilization of your imported blocks. You run sucsesfully a P&R with Quartus, but after downloding to FPGA the design did not work.
SYNPLIFY PRO MF515 ERROR SIMULATOR
How is it generated ? Did you run a simulation of the main project with the imported blocks included ? Which simulator do use for simulation Quartus or modelsim ?Ĥ. For your main project you need a toplevel. After solving some problems ( implementation as LE, switch from VHDL to verilog) the simulation shows the expected results.ģ. You run a simulation for each block using the vqm file generated by SynplifyPro. After that you import the two blocks into your main project as. Two blocks ( necessary due to the module name problems of SynplifyDSP). After that you run two speparate Quartus project in order to synthesis the You run two SynplifyDSP ( generates the VHDL ) and SynplifyPro (generates the vqm files) projects.
Is that memory outside of the FPGA or means "external" it is outside your original design ? How did you split the design ? In order to achieve timing closure you split your design and introduced an "external" memory. Pipeline delay in order to speedup the design ?Ģ. Is it not possible in SynplifyDSP to add some In this project you did not split your design,īut you don't get the required clock speed. Please post your comments to my points.ġ. Maybe it is now a good time where we should summarize what we know. Ps - not so much related - is there a way to automatically insert registers? Or must I register manually every connection? I want to remind you that my project was already working - except it didn't hold timing - when I combined the entire project in SynplifyDSP and not in Quartus (meaning - I combined before I synthesized) so I'm somewhat beliving that the problem is somewhere with my usage of the tools - not a design problem. What I see is that all my data outputs from the blocks are stuck at GND,Įven though input to it are correct (I used SignalTap to see these results)
But I don't use these parts, they are declared but that's it. My only conclusion - I must find a way to force the SynplifyDSP\PRO to generate different names, so I would be able to combine it all in Quartus, and thus hold the minimum frequency I need.Īs I'm using GiDEL card - I have many warnings that are related to their parts of the project (including timing error). I tried to combine the entire project into one file, but then when I choose retiming in synplify I didn't get the frequency I need (but when I synthesize each part on its own, I do get it to work fast enough). I think that this happens because Synplify DSP creates blocks with same names when working on different files. When I then compile the project, I get errors. This have created several VQM's that I then inserted into Quartus. I then synthesized each one separately (firstly I created VHDL in Synplify DSP and then went to Synplify PRO and ran a synthesis there). The problem I faced - In my algorithm I have to access external memory in between two parts of the algorithm, so to do so I divided my Synplify DSP project into several blocks (in several files), I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm.
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